1. Field of the Invention
Embodiments of the invention relate to the field of stress enhancements in the source/drain regions of transistors. More particularly, the present invention relates to a method for enhancing stress and source/drain activation using carbon ion implantation.
2. Discussion of Related Art
Current flowing through an electric field in the channel region of a field effect transistor is proportional to the mobility of the carriers (e.g., electrons in n-type field effect transistors (n-FETs) and holes in p-type field effect transistors (p-FETs)) in the channel region. Different strains on the channel region can effect carrier mobility and, thus, current flow. For example, compressive stress on a channel region of a p-FET can enhance hole mobility. Tensile stress on a channel region of an n-FET can enhance electron mobility. A number of stress engineering techniques are known for imparting the desired stress on n-FET and p-FET channel regions. For example, a compressive stress (i.e., a uni-axial compressive strain parallel to the direction of the current) can be created in the channel region of a p-FET by forming the source/drain regions with an alloy of silicon (Si) and germanium (Ge). A tensile stress (i.e., a uni-axial tensile strain parallel to the direction of the current) may be created in the channel region of an n-FET by forming the source/drain regions with an alloy of Si and carbon (C).
One problem with doping the source/drain region with an alloy containing C, however, is that the dopant ions (often arsenic (As) or phosphorus (P)) compete with the C ions for substitutional sites on the Si lattice, thus reducing the overall effectiveness of the dopant, and resulting in an increase in the sheet resistance (Rs) of the region, which undesirably reduces conductivity in the channel region.
Thus, there is a need for a method for creating strained Si:C layers that retain good conductivity (i.e. have desirably low sheet resistance) in the source/drain region, while also providing a desired tensile stress to enhance conductivity in the channel regions of semiconductor devices.